The invention relates to a semiconductor device and a method for forming a device isolation film in a semiconductor device.
As semiconductor devices become smaller, it is important to improve their operating speed via process development. As a result, many process technologies have been developed. Specifically, a process for forming a device isolation film in a DRAM is an important semiconductor manufacturing process.
Generally, the process for forming a device isolation film is a initial step in all semiconductor manufacturing processes to determine the size of an active region and the process margin of subsequent steps.
A Local Oxidation of Silicon (LOCOS) method has been widely used to form a device isolation film. However, the LOCOS process decreases the active region size due to a Bird's beak phenomenon that degrades the electrical characteristics of the device.
In order to prevent the degradation, a Shallow Trench Isolation (STI) process has been widely used to form a device isolation film.
The STI process results in poor trench gap fill characteristics and can cause trench voids. As a result, it is necessary to prevent the generation of voids.
FIGS. 1a to 1c are cross-sectional diagrams illustrating a conventional method for forming a device isolation film in a semiconductor device.
Referring to FIG. 1a, a pad oxide film and a pad nitride film are deposited over a semiconductor substrate 100. The resulting structure is selectively etched to form a pad oxide pattern 110 and a pad nitride pattern 120 that define a device isolating trench 130.
The semiconductor substrate 100 is dry-etched with the pad oxide pattern 110 and the pad nitride pattern 120 to form the device isolating trench 130.
Referring to FIG. 1b, a Spin-On-Dielectric (SOD) oxide film 140 is formed to fill a bottom portion of the trench 130.
The SOD oxide film 140 reduces the generation of voids resulting from filling defects in a narrow pattern region.
Referring to FIG. 1c, a High Density Plasma (HDP) oxide film 150 is formed over the SOD oxide film 140 to fill the remaining, upper portion of the trench 130.
A chemical-mechanical (CMP) process is performed to planarize the HDP oxide film 150 until the pad oxide pattern 120 is exposed.
As a result, a device isolation film is formed to have a deposition structure including the SOD oxide film 140 and the HDP oxide film 150 in the trench 130.
As mentioned above, a two-layered device isolation film inhibits generation of voids in a trench. However, if the critical dimension of a trench that defines the device isolation film is narrow, there is an increase the stress that an SOD oxide film applies to the sidewalls of the trench. As a result, the SOD oxide film applies a tensile stress to a PMOS semiconductor device and degrades the mobility of a carrier, thereby reducing the operating current of a DRAM device and degrading the electrical characteristics of a semiconductor device.